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Formal Checkers

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A tool for automatic generation of simulation monitors from formal specifications.
Product Details

FoCs takes properties written in the Sugar specification language and automatically translates them into Checkers, or monitors, which in turn are integrated into the chip simulation environment. These Checkers monitor the simulation results on a cycle-by-cycle basis for violation of the properties. Each Checker implements a state machine that enters and asserts an error state if the respective property fails to hold in a simulation run. This alphaWorks version is the first FoCs version that supports Sugar 2 (EDL flavor).

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Submitted on
15th January 2003
Last Updated
15th January 2003

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